1. Field of the Invention
The invention relates in general to analog/digital converters (ADCs) and in particular to a method and apparatus for timing background calibration in an ADC.
2. Description of Related Art
FIG. 1 depicts a typical prior art, self-calibrating, analog-digital converter (ADC) 22 for digitizing an analog input signal X to produce a digital data sequence Y= representing the voltage of signal X at successive edges of a clock signal CLK. Input signal X passes through a switch 24 to the input of an ADC 26. In response to each edge of clock signal CLK, ADC 26 samples signal X and produces a “raw”, uncalibrated, digital output sequence Y supplied as input to a calibration circuit 28. For example, calibration circuit 28 may act as a lookup table, altering the value of each element of sequence Y= as necessary to compensate for errors in the output sequence Y of ADC 26, thereby to produce a corresponding element of output sequence Y=. During a calibration process, a calibration control circuit 30 supplies a reference signal VREF of various known voltages as input to ADC 26 via switch 24, monitors ADC output Y to determine its error, and supplies programming data to calibration circuit 28 configuring it to appropriately compensate for detected errors in Y. While FIG. 1 depicts an ADC 22 including a calibration circuit 28 for altering the output of ADC 26, other self-calibrating ADCs use other approaches to calibration. For example, calibration control circuit 30 could calibrate ADC 26 by adjusting the gain and offset of an input amplifier within ADC 26, thereby eliminating the need for calibration circuit 28.
The errors in the output of ADC 26 arise due to various “non-ideal” effects associated with its internal components, including the settling time of its internal sample and hold amplifier, the finite gain and offset of its internal amplifier(s), and reflections and other effects due to component mismatches. These sources of error typically limit the speed and accuracy of ADC 26 and impose stringent requirements on its component design that can prolong design time and increase hardware cost. By compensating for errors in the output of ADC 26, calibration circuit 28 can reduce the severity of the ADC=s component design requirements, thereby reducing design time and hardware cost.
ADC calibration techniques fall into two categories: foreground calibration and background calibration. ADC 22 of FIG. 1 employs foreground calibration wherein calibration control circuit 30 calibrates ADC 22 only once, during a start-up period following power-on when ADC 22 is not actively digitizing input signal X to produce output sequence Y=. After programming calibration circuit 28, calibration control circuit 30 signals switch 24 to supply input signal X to ADC 26 so that ADC 22 enters its normal mode of operation, continuously digitizing input signal X to produce output sequence Y=. The main drawback to foreground calibration is that since the ADC is calibrated only once at startup, the ADC can drift out of calibration over time. Operating characteristics of components of ADC 26 can change over time, for example due to temperature changes and circuit aging, and such changes can cause the error in output data sequence Y to drift. ADCs employing background calibration repeatedly carry out the calibration process “in the background” while the ADC is digitizing an analog input signal to update ADC calibration from time-to-time to compensate for drift in ADC error.
FIG. 2 illustrates a prior art self-calibrating ADC 31 employing a form of background calibration. Here the analog signal X being digitized provides an input to a high-speed, but inaccurate, ADC 32 as well as to a lower speed, but highly accurate, ADC 34. A calibration circuit 36 modifies the output sequence Y of ADC 32 to compensate for errors, thereby to produce the digitizer output sequence Y=. A calibration control circuit 38 compares each element of the output sequence Yr of ADC 34 to an element of output sequence Y of ADC 32 representing a concurrently acquired sample of input signal X to determine the error in sequence Y and then appropriately adjusts the programming of calibration circuit 36. This approach has the disadvantage of requiring a highly accurate ADC 34 not subject to errors that drift over time, and such an ADC can be difficult and expensive to design and implement. U.S. Pat. No. 6,606,042 issued Aug. 12, 2003 to Sonkusale et al teaches this type of background calibration method in the context of a pipelined ADC.
The article by I. Galton, “Digital Cancellation of D/A Converter Noise in Pipelined A/D converters,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47 no. 3, pp. 185-196, March 2000, discusses another approach to background calibration wherein a known pseudo-random reference signal is added to the normal analog input to produce a modified input to the ADC. The value of the reference signal is then subtracted from the raw ADC output data to produce the digital data representing the analog input signal. A calibration control circuit uses statistical analysis techniques to extract the ADC error from the raw ADC output data so that it can determine how to appropriately adjust the raw data to compensate for the ADC error. One disadvantage to this approach is that adding the reference signal to the input signal reduces the usable dynamic range of the normal input.
According to sampling theory, the information carried by an analog signal can be fully preserved by discrete-time samples when an ADC=s sampling rate is higher than twice the highest frequency components of the signal. For a “Nyquist rate” ADC, the sampling rate just meets that criterion. When an ADC uses a sampling rate higher than needed, it has extra resources available to do the calibration in the background. Once in a while it can replace the normal analog input signal with a reference signal of known magnitude to check the ADC=s error. The ADC later fills in the output data sequence with output data representing the sample of the normal analog input signal that was “skipped” during the calibration cycle by interpolating preceding and subsequent sample values. This “skip and fill” type of background calibration works well but adds overhead by requiring a higher than normal sampling speed.
FIG. 3 depicts a self-calibrating ADC 42 employing skip and fill background calibration. A switch 44 normally passes analog input signal X to an ADC 46 producing output sequence Y. A delay circuit 48 delays Y by a number of clock cycles to produce an output sequence Ya. A switch 50 normally supplies sequence Ya as an input sequence Yb to a calibration circuit 52 programmed to adjust values of elements of sequence Yb to compensate for errors in sequence Y caused by ADC 46. A timer circuit 54 periodically sends a SKIP signal to a calibration control circuit 56 telling it to carry out a calibration procedure wherein it supplies a known reference voltage as input to ADC 46 via switch 44 in place of input signal X for one cycle of clock signal CLK so that calibration control circuit 56 can monitor Y and adjust the programming of calibration circuit 52 as necessary. During each clock cycle in which ADC 46 receives reference signal VREF, rather than input signal X, ADC output signal Y will reflect the magnitude of VREF rather than the magnitude of input signal X. Delay circuit 48 delays Y for K cycles of clock signal CLK, so during the Kth clock cycle following a cycle in which ADC 46 digitizes VREF, the value of the current element of sequence Ya will reflect the magnitude of reference signal VREF rather than input signal X. Calibration control circuit 56 therefore signals switch 50 to pass the output Yc of an interpolation filter 58, rather than Ya as input Yb to calibration circuit 52. Interpolation filter 58 uses interpolation to estimate an appropriate value of the current element of Yc as a function of values of proceeding and succeeding elements of the Y sequence. The K cycle delay of the delay circuit 48 matches the processing latency of the interpolation filter 58. For example, FIG. 4 shows the value of Yb as a function of time in a case where calibration control circuit 56 performs a calibration operation on every fourth cycle of the CLK signal. Thus, interpolation filter 58 provides the value of Yc on clock cycles 4, 8, 12, 16, and 20 although in practice, the calibration process is carried out much less frequently. Since changes in error of ADC 46 normally occur relatively slowly, the average time between calibration cycles can usually be made quite long without significantly affecting the ability of the calibration process to compensate for changes in ADC 46.
U.S. Pat. No. 6,473,012 discloses a “randomized timing” type of skip and fill background calibration. To implement that kind of skip and fill background calibration, timer 54 could be a random or pseudo-random time interval generator that asserts the SKIP signal with randomly or pseudo-randomly varying time intervals. Thus, as illustrated in FIG. 5, calibration cycles might occur, for example, at times 2, 5, 10, 14, and 20. Randomized timing skip and fill background calibration avoids overlooking any periodic error pattern in Y that could be missed using a fixed timing skip and fill background calibration technique.
In either type of skip and fill background calibration, interpolation filter 58 estimates the values of skipped samples of input signal X based on values interpolated from neighboring samples. The interpolated values will have some error, but if a highly accurate, finite impulse response (FIR) filter with many taps implements interpolation filter 58, the interpolation errors can be very small. However, a high performance interpolation filter 58 not only requires substantial hardware but also introduces long latency because it has to buffer sample data over a long period before and after a skipped sample to accurately interpolate the skipped value.
What is needed is an ADC using skip and fill background calibration that can achieve relatively high interpolation accuracy using an interpolation filter having a relatively small number of taps and having a relatively short latency.